In current semiconductor industry, integrated circuit (IC) products are divided into three main types including logic, memory, and analog circuit. Memory devices account for a significant portion of IC products. Memory devices include, e.g., random access memory (RAM), dynamic random access memory (DRAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory (FLASH) and ferroelectric RAM (FRAM), etc. Flash memory devices have had especially rapid development. Main features of flash memory devices include a number of advantages such as ability of long-term information storage without electric power, high degree of integration, fast access speed, and ease of erasing. Thus, flash memory devices are widely applied in many areas such as microcomputers, and automated control. Flash memory structure generally includes a floating gate and a control gate.
FIGS. 1-4 depict cross-sectional views of a floating gate structure of a conventional flash memory device at various stages during its formation. Referring to FIG. 1, a semiconductor substrate 10 is provided. An oxide layer 20 on the surface of the semiconductor substrate 10, and a silicon nitride layer 30 on the surface of the oxide layer 20, are sequentially formed. An opening is formed in the oxide layer 20 and the silicon nitride layer 30. The semiconductor substrate 10 is etched along the opening to form a groove. The groove is filled with silicon oxide to form an isolation structure 40. The surface of the isolation structure 40 is leveled with the surface of the silicon nitride layer 30.
Referring to FIG. 2, the silicon nitride layer 30 (in FIG. 1) is removed, to expose a portion of the isolation structure 40 located above the oxide layer 20. Referring to FIG. 3, a polysilicon layer 50 is formed on the surface of the oxide layer 20 and the isolation structure 40. The polysilicon layer 50 fills a gap between adjacent isolation structures 40.
Refer to FIG. 4, the polysilicon layer 50 is planarized to form a polysilicon layer 51 after the planarization. The surface of polysilicon layer 51 (i.e., the polysilicon layer 50 after the planarization) is leveled with the surface of the isolation structure 40. The polysilicon layer 51 and the oxide layer 20 beneath the polysilicon layer 51 thus form a floating gate structure.
However, under currently used processes, the polysilicon layer of the conventional floating gate structure tends to have voids. Performance of a subsequently-formed flash memory device can thus be affected. The disclosed methods and structures are directed to solve one or more problems set forth above and other problems.